1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, it relates to an electrically programmable and erasable nonvolatile semiconductor memory device (hereinafter referred to as a flash memory) including stack gate type memory cells and an operating method thereof.
2. Description of the Background Art
First, general definitions of erasing and programming are described. Erasing means an operation of batch-changing the threshold voltages of a plurality of memory cells to prescribed states. Programming means an operation of changing the threshold voltage of selected memory cells to another prescribed state. Data "1" corresponds to an erased memory cell, and data "0" corresponds to a programmed memory cell.
(1) Sectional Structure of Memory Cell (FIGS. 128 and 129)
FIG. 128 shows a sectional structure of a general stack gate type memory cell (memory transistor) which is employed in a conventional flash memory. A P.sup.- -type semiconductor substrate 1001 is provided on its major surface with two N.sup.+ -type impurity regions, which form a drain 1002 and a source 1003 respectively, at a prescribed interval. An extremely thin insulating film 1004 (about 100 .ANG. in thickness) of an oxide film or the like is formed on a region of the semiconductor substrate 1001 between the drain 1002 and the source 1003. A floating gate 1005 is formed on the insulating film 4, while a control gate 1006 is formed thereon with another insulating film interposed therebetween. Thus, the memory cell has a double gate structure. The P.sup.- -type semiconductor substrate 1001 may be replaced by a P.sup.31 well.
In the flash memory, information (data) is stored in the memory cell depending on whether electrons are injected into or emitted from the floating gate 1005.
When electrons are injected into the floating gate 1005, the threshold voltage of the memory cell as viewed from the control gate 1006 is so high that no current flows across the drain 1002 and the source 1003 unless the control gate voltage exceeds Vg0, as shown in FIG. 129. This is because negative charges of the electrons stored in the floating gate 1005 cancel a positive voltage. This state is called a programmed state. In this case, the memory cell stores the data "0". The electrons stored in the floating gate 1005 semipermanently remains unerased, whereby the stored data is also semipermanently held.
When electrons are emitted from the floating gate 1005, on the other hand, the threshold voltage of the memory cell as viewed from the control gate 1006 is so low that a current flows across the drain 1002 and the source 1003 when the control gate voltage exceeds Vg1, as shown in FIG. 129. This state is called an erased state. In this case, the memory cell stores data "1".
It is possible to read the data stored in the memory cell by detecting the aforementioned two states.
(2) Programming and Erasing of Memory Cell (FIG. 130)
FIG. 130 shows conditions of voltage application for programming and erasing the memory cell at (a) and (b) respectively.
In programming, a write voltage Vw (about 6 V in general) is applied to the drain 1002 and a high voltage Vpp (about 12 V in general) is applied to the control gate 1006, while the source 1003 is grounded. Thus, hot electrons are generated in the vicinity of the drain 1002 by avalanche breakdown, or channel hot electrons having high energy are generated in a channel formed in the region between the drain 1002 and the source 1003. The hot electrons accelerated by the high voltage of the control gate 1006 jump over an energy barrier formed by the insulating film 1004, to be injected into the floating gate 1005 from a portion close to the drain 1002. As the result, the threshold voltage of the memory cell is increased.
In erasing, on the other hand, the drain 1002 is brought into a floating state and a high voltage Vpp is applied to the source 1003, while the control gate 1006 is grounded. Thus, a high voltage is generated in the thin insulating film 1002, so that the electrons are emitted from the floating gate 1005 to the source 1003 by a tunnel effect. As the result, the threshold voltage of the memory cell is reduced.
Thus, electrons are injected into the floating gate 1005 by hot electrons in programming. As shown in FIG. 130, therefore, a P.sup.+ -type impurity region 1002a is provided along the drain 1002 so that a higher electric field is generated in the channel or substrate direction.
In erasing, on the other hand, electrons are emitted from the floating gate 1005 to the source 1003 by a tunnel effect. Thus, only an electric field generated across the floating gate 1005 and the source 1003 is required for such erasing. The electric field in the channel or substrate direction is preferably minimized to cause no leakage current. Therefore, an N.sup.- -type impurity region 1003a is provided along the source 1003, in order to weaken the electric field in the channel or source direction.
(3) Overall Structure of Flash Memory (FIGS. 131 and 132)
FIG. 131 is a block diagram showing the overall structure of the conventional flash memory.
A memory array 1010 includes a plurality of bit lines, a plurality of word lines crossing with the plurality of bit lines, and a plurality of memory cells which are provided on the crossings.
FIG. 131 shows only four memory cells M00, M01, M10 and M11 which are arranged in two rows and two columns, for simplifying the illustration. Drains of the memory cells M00 and M01 are connected to a bit line BL0, while those of the memory cells M10 and M11 are connected to another bit line BL1. Control gates of the memory cells MOO and M10 are connected to a word line WL0, while those of the memory cells M01 and M11 are connected to another word line WL1. Sources of the memory cells M00, M01, M10 and M11 are connected to a source line SL.
An address buffer 1020 receives externally supplied address signals AD, to supply X and Y address signals to X and Y decoders 1030 and 1040 respectively. The X decoder 1030 selects one of the plurality of word lines WL0 and WL1 in response to the X address signal. On the other hand, the Y decoder 1040 generates a selection signal Y0 or Y1 for selecting one of the plurality of bit lines BL0 and BL1 in response to the Y address signal.
A Y gate 1050 includes Y gate transistors YG0 and YG1 in correspondence to the bit lines BL0 and BL1. The Y gate transistors YG0 and YG1 connect the bit lines BL0 and BL1 to a sense amplifier 1060 and a write circuit 1080 in response to the selection signals Y0 and Y1 respectively.
In reading, the sense amplifier 1060 detects data read on the bit line BL0 or BL1, and outputs the same to the exterior through a data input/output buffer 1070. In programming, on the other hand, externally supplied data DA is supplied to the write circuit 1080 through the data input/output buffer 1070, so that the write circuit 1080 supplies a write voltage to the bit lines BL0 and BL1 in accordance with the data DA.
A Vpp/Vcc switching circuit 1090 receives an externally supplied high voltage (12 V in general) and an externally supplied power supply voltage Vcc (5 V in general), and supplies the X decoder 1030, the Y decoder 1040 and the write circuit 1080 with the high voltage Vpp or the power supply voltage Vcc. A verify voltage generating circuit 1100 receives the externally supplied power supply voltage Vcc, and supplies a prescribed verify voltage to a selected word line in verification as described later. A source control circuit 1110 supplies the source line SL with the high voltage Vpp in erasing.
A control signal buffer 1012 supplies an externally supplied control signal CT to a control circuit 1130, which controls operations of the respective circuits.
As shown in FIG. 132, the X decoder 1030 includes a decoder circuit 1301, and a plurality of high voltage switches 1302 corresponding to the plurality of word lines WL. The decoder circuit 1301 decodes an X address signal XA, to generate a selection signal for selecting one of the plurality of word lines WL. Each high voltage switch 1302 supplies the selected word line WL with the high voltage Vpp or the power supply voltage Vcc in response to a control signal SW received from the control circuit 1130.
This flash memory is formed on a chip CH.
(4) Operation of Flash Memory (FIGS. 133 to 140)
(a) Program Operation (FIG. 133)
FIG. 133 illustrates conditions of voltage application in a program operation. It is assumed here that the memory cell M00 is programmed, for example. The control circuit 1130 is supplied with a control signal specifying a program operation through the control signal buffer 1120. The Vpp/Vcc switching circuit 1090 is supplied with a high voltage Vpp from the exterior, and supplies the same to the X and Y decoders 1030 and 1040.
The X decoder 1030 selects the word line WL0 in response to an X address signal received from the address buffer 1020, to supply the high voltage Vpp to the same.
The Y decoder 1040 supplies a high voltage selection signal Y0 to the Y gate transistor YG0 in response to a Y address signal received from the address buffer 1020. Thus, the Y gate transistor YG0 is turned on.
The source control circuit 1110 supplies 0 V to the source line SL. The write circuit 1080 is activated. Thus, the write voltage Vw is supplied to the bit line BL0.
As the result, voltages are applied to the memory cell M00 as shown at (a) in FIG. 130, to program the memory cell M00.
(b) Erase Operation (FIGS. 134 to 136)
An erase operation includes a pre-erase write operation and a batch erase operation.
(i) Pre-Erase Write Operation (FIG. 134)
Before batch erasing of memory cells, all memory cells are programmed by the aforementioned method. Thus, the threshold voltages of all memory cells are increased. This is called a pre-erase write operation.
With reference to a flow chart shown in FIG. 134, the pre-erase write operation is now described. First, a determination is made as to whether or not data stored in all memory cells are "0" (step S51). If data of all memory cells are not "0", an address specified by an address signal is set at zero (step S52). The memory cell specified by the address signal is programmed by the aforementioned program operation (step S53).
Then, a determination is made as to whether or not the address specified by the address signal is the final one (step S54). If the address is not the final one, the addresses are incremented one by one (step S55), to carry out a program operation (step S53). This operation is continued until the final address is reached (steps S53, S54 and S55). When the final address is reached, the pre-erase write operation is terminated.
(ii) Batch Erase Operation (FIGS. 135 and 136)
A batch erase operation is now described with reference to a flow chart shown in FIG. 135. FIG. 136 shows conditions of voltage application for the batch erase operation.
First, a control signal specifying batch erasing is supplied to the control circuit 1130 through the control signal buffer 1120. In batch erasing, the Vpp/Vcc switching circuit 90 supplies the high voltage Vpp to the source control circuit 1110, which in turn supplies the high voltage Vpp to the source line SL (step S61).
The X decoder 1030 grounds the word lines WL0 and WL1. On the other hand, the Y decoder 1040 supplies selection signals Y0 and Y1 of 0 V to the Y gate transistors YG0 and YG1 respectively. Thus, the bit lines BL0 and BL1 enter floating states.
As the result, voltages are applied to all memory cells as shown at (b) in FIG. 130, whereby the threshold voltages of all memory cells are reduced.
It is difficult to reduce the threshold voltages of all memory cells below a prescribed value only by one time application of the high voltage (erasing voltage) to the source line SL. In general, therefore, high voltage pulses are applied to the source line SL a plurality of times, and erase verification is performed after every pulse application.
First, a high voltage pulse is applied to the source line SL (step S61), and thereafter the source line SL is set at 0 V (step S62), to select an address zero (step S63). Then, a prescribed verify voltage which is lower than the power supply voltage Vcc is supplied to the selected word line by the verify voltage generating circuit 1100 (step S64). Thus, data is read from the selected memory cell on a corresponding bit line, to be detected by the sense amplifier 1060. Then, a determination is made as to whether or not the data detected by the sense amplifier 1060 is "1" (step S65).
If the data detected by the sense amplifier 1060 is "0", the steps S61 to S64 are repeated.
If the data detected by the sense amplifier 1060 is "1", on the other hand, a determination is made as to whether or not an address specified by an address signal is the final one (step S66). If the address is not the final one, this address is incremented by 1 (step S67). Thus, data are read out from all memory cells while the addresses are incremented one by one. If a read data is "0", a high voltage pulse is applied to the source line SL, to erase the memory cell.
Thus, the threshold voltages of the memory cells are monitored so that all memory cells are gradually erased.
(c) Read Operation (FIG. 137)
FIG. 137 shows conditions of voltage application for a read operation. It is assumed here that data is read out from the memory cell M00.
First, a control signal specifying a read operation is supplied to the control circuit 1130 through the control signal buffer 1120. The X decoder 1030 selects the word line WL0 in response to an X address signal received from the address buffer 1020, and applies the power supply voltage Vcc to the same. At this time, the potential of the nonselected word line WL1 is maintained at 0 V.
The Y decoder 1040 turns on the Y gate transistor YG0 in response to a Y address signal received from the address buffer 1020. Thus, the bit line BL0 is connected to the sense amplifier 1060. At this time, the source control circuit 1100 supplies 0 V to the source line SL.
As the result, the memory cell M00 enters an ON state when its threshold voltage is low. Thus, a current I flows in a resistor R provided in the sense amplifier 1060, to reduce a read voltage Vr on the bit line BL0. The read voltage Vr on the bit line BL0 is outputted as data "1" through an inverter INV2.
When the threshold voltage of the memory cell M00 is high, on the other hand, the memory cell m00 enters an OFF state. Thus, the read voltage Vr on the bit line BL0 is high. The read voltage Vr on the bit line BL0 is outputted as data "0" through the inverter INV2.
When the voltage of a bit line approaches the power supply voltage Vcc in reading, hot electrons may be generated to program the memory cell. This is called asoft write phenomenon. In order to prevent the soft write phenomenon, the read voltage Vr on the bit line is set at about 1 V by an N-channel transistor TR and an inverter INV1.
(d) Potentials on Respective Lines in Respective Operations (FIG. 138)
FIG. 138 shows potentials on word, bit and source lines in program, erase and read operations. In program and pre-erase write operations, the high voltage Vpp is applied to the word line and the write voltage Vw is applied to the bit line while 0 V is applied to the source line. In batch erasing, the high voltage Vpp is applied to only the source line and 0 V is applied to the word line, while the bit line is in a floating state. In reading, the source voltage Vcc is applied to the word line and the source line is at 0 V, while the read voltage Vr appears on the bit line.
(3) Reason for Requirement for Pre-Erase Write Operation (FIGS. 139 and 140)
The reason why the pre-erase write operation is required in erasing is now described with reference to FIGS. 139 and 140. FIG. 139 shows changes in the threshold voltage of the memory cell caused by program and batch erase operations. FIG. 140 shows changes in the threshold voltage of the memory cell caused by program, pre-erase write and batch erase operations.
In the batch erase operation, the control gate 1006 reaches 0 V and the drain 1002 enters a floating state while the source 1003 is supplied with the high voltage Vpp in the memory cell, as shown at (b) in FIG. 130. In such conditions of voltage application, a high voltage is developed across the source 1003 and the floating gate 1005, whereby the electrons stored in the floating gate 1005 are extracted to the source 1003. As the result, the threshold voltage of the memory cell is reduced.
If this erase operation is carried out in a low threshold voltage state (data "1"), however, the threshold voltage of the memory cell reaches a negative value, as shown in FIG. 139. This is called depression of the memory cell, which causes the following problem in reading:
It is assumed here that the memory cell M00 is selected in the read operation shown in FIG. 137 while the memory cell M01 is depressed by batch erasing. Namely, the threshold voltage of the memory cell m01 is at a negative value.
In this case, the source voltage Vcc is applied to the word line WL0, while the potential of the word line WL1 remains at 0 V. If the memory cell M00 stores data "0", this memory cell M00 is not turned on even if the potential of the word line WL0 reaches the power supply voltage Vcc. Thus, no current is generated in the bit line BL0.
When the threshold voltage of the memory cell M01 is at a negative value, however, this memory cell M01 is turned on even if the potential of the word line WL1 is at 0 V. As the result, a current is generated on the bit line BL0. In this case, the sense amplifier 1060 determines that the memory cell M00 stores data "1".
When at least one of memory cells which are connected to a bit line has a negative threshold voltage, as hereinabove described, a current inevitably flows in the bit line even if the memory cell is in a nonselected state. Thus, the data stored in the selected memory cell cannot be correctly read.
In order to solve such a problem, the pre-erase write operation is carried out before the batch erase operation, as shown in FIG. 140. Thus, the threshold voltages of all memory cells are temporarily brought into high states, so that the batch erase operation is thereafter carried out. As the result, the voltages of the erased memory cells are unified at positive values which are lower than the power supply voltage Vcc. Thus, reliability of the memory is improved by the pre-erase write operation.
However, the conventional flash memory has the following problems:
(1) Rewrite Operation (FIG. 141)
In order to rewrite data stored in the memory cells in the aforementioned conventional flash memory, as shown in FIG. 141, a pre-erase write operation is carried out (step S71) and then a batch erase operation is carried out (step S72), so that a program operation is thereafter carried out (step S73).
When the capacity of the flash memory is increased, a time required for the pre-erase write operation is extremely increased. For example, a flash memory of 1001 megabit requires 1001 to 1002 seconds for programming memory cells of all addresses.
When the pre-erase write operation requires such a long time, it means that a long time is required for rewriting the data. This is extremely inconvenient for the user.
(2) Depression by Over-Erasing (FIGS. 142 and 143)
In erasing, the pre-erase write operation is carried out in advance of the batch erase operation in order to unify the threshold voltages of the memory cells substantially at the same values, as hereinabove described. In practice, however, a plurality of memory cells provided in an erase unit are necessarily dispersed in erasability.
If such dispersion is extremely large as shown in FIG. 142, parts of the memory cells are over-erased and depressed.
In such depressed memory cells, currents inevitably flow even if the control gates thereof are grounded. As the result, data read from memory cell which is connected to the same bit line as the depressed memory cell is so disturbed by the depressed memory cell that the data thereof is regularly determined as "1".
FIG. 143 shows the structure of a memory cell having no such problem.
Referring to FIG. 143, a P.sup.- -type semiconductor substrate 301 is provided on its major surface with N.sup.+ -type impurity regions 1302, 1303 and 1310 at prescribed intervals. A gate electrode 1304 is formed on a region between the impurity regions 1302 and 1303 with an insulating film formed by an oxide film interposed therebetween. Thus, a selection transistor 1305 is constituted. A floating gate 1307 is formed on the impurity region 1303 with an extremely thin oxide film 1306 of about 100 .ANG. interposed therebetween, and a control gate 1308 is formed thereon with another insulating film interposed therebetween. Thus, a memory transistor 1309 having a two-layer gate structure is constituted.
The selection transistor 1305 and the memory transistor 1309 form a one-bit memory cell. The impurity region 1302 is connected to a bit terminal B, while the gate electrode 1304 is connected to a word terminal W. The impurity region 1310 is connected to a source terminal S. The control gate 1308 is connected to a control gate terminal CG.
The memory cell shown in FIG. 143 is provided with the selection transistor 1305, whereby no problem is caused even if the memory transistor 1309 is depressed, dissimilarly to the above.
However, the memory cell shown in FIG. 143 is complicated in structure as compared with the stack gate type memory cell shown in FIG. 128, and requires a wide area.
(3) Disturbance between Sectors (FIG. 144)
In a conventional flash memory, it is possible to subdivide a data rewrite unit by sectoring a memory array. In this case, however, a memory cell provided in a selected sector disadvantageously influences that provided in a nonselected sector. This phenomenon is called disturbance.
Consider that a plurality of memory cells which are connected to a word line WL0 are divided into selectors SE1 and SE2 as shown in FIG. 144, for example. In this case, a high voltage is applied also to a control gate of a memory cell provided in the nonselected sector SE2 when a memory cell provided in the sector SE1 is programmed.
On the other hand, consider that a plurality of memory cells which are connected to a bit line BL0 are divided into sectors SE1 and SE3. In this case, a high voltage is applied also to a drain of a memory cell provided in the nonselected sector SE3 when the memory cell provided in the sector SE1 is programmed.
In each case, it is possible to sufficiently guarantee data even if the disturbance is repeated thousands of times. Assuming that data in a memory cell provided in a single sector is rewritten by 10000 times, however, disturbance is caused in another sector by the following number of times, since a plurality of sectors are provided on the same word line and the same bit line: EQU Disturbance=(10000 times).times.(number of sectors-1)
Thus, disturbance is caused in a sector by an enormous number of times when a plurality of sectors are present. In recent years, however, such a sector must guarantee a great number of rewrite times. Thus, the disturbance between different sectors is extremely problematic.
(4) Power Consumption
When a memory cell is programmed in a conventional flash memory, electrons are injected into its floating gate by channel hot electrons. Thus, a large channel current is required for programming, leading to increase in power consumption.
(5) Integration Density
A conventional flash memory is disclosed having a main bit line and a subbit line in U.S. Pat. No. 5,126,808. In such a flash memory, electrons are drawn by channel hot electrons for programming to result in a great channel current. This will generate a problem set forth in the following.
FIG. 145 is a layout of a conventional flash memory having a main bit line and a subbit line on a semiconductor substrate. Referring to FIG. 145, a main bit line MB and subbit lines SB0 and SB1 are formed in parallel on a semiconductor substrate. Word lines WL0, WL1, . . . and select gate lines SGL0, SGL1 are formed in a direction perpendicular to the bit lines. A memory cell is formed at each crossing of a word line and a subbit line. For example, memory cells M11, M12, . . . are formed at the crossings of each of the word lines WL0, WL1, . . . and the subbit line SB1. A select gate transistor SG' for sector selection is formed at the crossing of the main bit line MB and the select gate line SGL0. An N.sup.+ diffusion layer 1405 is formed in the semiconductor substrate.
In memory cells M11, M12, . . . shown in FIG. 145, programming using channel hot electrons is carried out as described above to result in a great channel current flowing via the subbit line SB1. Because this great current flows via the select gate transistor SG' for sector selection, it is necessary to select a great value of a channel width for select gate transistor SG'. This means that a select gate transistor SG' occupies a large area on a semiconductor substrate, resulting in reduction of the integration density in a semiconductor substrate.
Furthermore, the flash memory shown in FIG. 145 has first and second aluminum interconnection layers formed as the subbit lines SB0, SB1 and the main bit line MB in order to reduce the resistance of the main bit line MB and the subbit lines SB0 and SB1. This means that an aluminum interconnection layer can not be used to reduce the resistance of word lines WL0, WL1, . . . formed by a polysilicon layer. As a result, there will be a delay in the transfer of a signal in a word line, so that a high operation speed can not be obtained.
FIG. 146 is a structure of a memory cell of a conventional flash memory. Referring to FIG. 146, two memory cells M00 and M10 are isolated by an isolation oxide film 1402 formed on a P well 1008. For example, when programming is to be carried out for memory cell M10, high voltage of 10V is applied to a second aluminum interconnection layer 1006 forming a control gate and a voltage of 5V is applied to a drain 1002' of transistor M10. A width Wb of isolation oxide film 1402 too narrow is equivalent to the presence of a MOS transistor 1403 using this isolation oxide film 1402 as a gate oxide film. The presence of an equivalent MOS transistor 1403 will prevent a desired operation in memory cells M00 and M10. Therefore, the width Wb of isolation oxide film 1402 can not be set to a low value in order to prevent generation of this equivalent MOS transistor 1403. This means that the integration density in the memory cell array is reduced.
FIG. 147 is a circuit diagram showing the voltage applied to the memory cell array of a conventional flash memory. FIG. 147(a) shows the voltage applied for programming, and FIG. 147(b) shows the voltage applied for erasure.
Referring to FIG. 147(a), a voltage of 5V is applied to the bit line BL0 and a negative voltage of -10V is applied to the word line WL11 to introduce electrons into the floating gate of memory cell M00. The non-selected word line WL12 is applied with a voltage of 5V. In other words, the X decoder not shown must provide voltages of -10V and 5V.
Referring to FIG. 147(b), a positive voltage of 10V is applied to word lines WL11 and WL12, and bit lines BL0 and BL1 are brought to a high impedance state in order to erase the data stored in the selected sector SE1. A negative voltage of -8V is applied to word lines WL21 and WL22 in the non-selected sector SE2. In other words, the X decoder not shown must provide a positive voltage of 10V and a negative voltage of -8V.
Therefore, the X decoder not shown must provide an output voltage having a voltage difference of 15V in a programming operation, and a voltage difference of 18V in an erase operation. Because the voltage difference of the output voltage is great, it is difficult to form the X decoder on a smaller area on a semiconductor substrate.
(6) External Power Supply
In programming, it is necessary to apply a voltage of 1005 to 1006 V to the drain of each memory cell. Since programming by the channel hot electrons requires a large channel current as described above, it is extremely difficult to produce such a drain voltage by internal voltage boost through a single external power supply of 1003 or 5 V. Even if the drain voltage can be produced, it is impossible to simultaneously program a number of bits. Thus, the program time is extremely increased.
(7) Structure of Conventional Flash Memory
The structure of a conventional flash memory will be described in detail.
A flash memory is known as a memory device in which data can be freely written and can be electrically erased. An EEPROM including one transistor and allowing collective erasure of charges representing written information electrically, that is, a so called flash memory has been proposed in U.S. Pat. No. 4,868,619 and in "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory" by Virgil Niles Kynett et al., IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, October 1988.
FIG. 148 is a block diagram showing a general structure of a flash memory. Referring to the figure, the flash memory includes a memory cell matrix 1 arranged in rows and columns, an X address decoder 2, a Y gate 3, a Y address decoder 4, an address buffer 5, a write circuit 6, a sense amplifier 7, an input/output buffer 8 and a control logic 9.
Memory cell matrix 1 has a plurality of memory transistors arranged in rows and columns formed therein. X address decoder 2 and Y gate 3 are connected to select a row and a column of memory cell matrix 1. Y address decoder 4 for applying information to select the column is connected to Y gate 3. X address decoder 2 and Y address decoder 4 are connected to address buffer 5 in which address information is temporarily stored.
Y gate 3 is connected to write circuit 6 for effecting writing operation at the time of data input and to sense amplifier 7 for determining "0" and "1" from the current value flowing at the time of data output. Write circuit 6 and sense amplifier 7 are connected to input/output buffer 8 for temporarily storing the input/output data. Address buffer 5 and input/output buffer 8 are connected to control logic 9 for controlling operation of the flash memory. Control logic 9 controls in accordance with a chip enable signal, an output enable signal and a program signal.
FIG. 149 is an equivalent circuit diagram showing the schematic structure of the memory cell matrix 1 shown in FIG. 148. The flash memory having this memory cell matrix is referred to as an NOR type one. Referring to the figure, a plurality of word lines WL.sub.1, WL.sub.2, . . . , WL.sub.i extending in the row direction and a plurality of bit lines BL.sub.1, BL.sub.2, . . . , BL.sub.j extending in the column direction are arranged to cross orthogonally with each other, thus forming a matrix. Memory transistors Q.sub.11, Q.sub.12, . . . Q.sub.ij each having a floating gate are arranged at crossings between the word lines and the bit lines. Each memory transistor has its drain connected to the bit line. Each memory transistor has its control gate connected to the word line. The memory transistors have their sources connected to respective source lines S1, S2, . . . . The sources of the memory transistors belonging to the same row are connected to each other as shown in the figure.
FIG. 150 is a partial cross section showing a cross sectional structure of one memory transistor forming the above-described NOR type flash memory. FIG. 151 is schematic plan view showing the planar layout of the NOR type flash memory. FIG. 152 is a partial cross section taken along the line A--A of FIG. 151. The structure of the NOR type flash memory will be described with reference to the figures.
Referring to FIGS. 150 and 152, in a p type impurity region 10 formed in a silicon substrate, n type impurity regions, for example a drain region 11 and a source region 12 are formed spaced apart from each other. A control gate 13 and a floating gate 14 are formed at the region sandwiched by the drain region 11 and source region 12 so that a channel is formed. Floating gate 14 is formed on p type impurity region 10 with a thin gate oxide film 15 having the thickness of about 100 .ANG. posed therebetween. Control gate 13 is formed on floating gate 14 with an interlayer insulating film 16 posed therebetween so that it is electrically separated from the floating gate 14. Floating gate 14 is formed of polycrystalline silicon. Control gate 13 is formed of polycrystalline silicon layer or a stacked layer including polycrystalline layer and a layer of a metal having high melting point. Oxide film 17 is formed by deposition by the CVD method on the surface of the polycrystalline silicon layer forming floating gate 14 or control gate 13. A smooth coat film 21 (see. FIG. 91) is formed to cover floating gate 14 and control gate 13.
As shown in FIG. 151, control gates 13 are formed to be connected with each other to extend in the lateral direction (row direction), serving as a word line. The bit line 18 is arranged to orthogonally cross word line 13, and is electrically connected to each drain region 11 through a drain contact 20. As shown in FIG. 152, bit line 18 is formed on smooth coat film 21. As shown in FIG. 151, source region 12 extends in the direction along the word line 13 and is formed at a region surrounded by word line 13 and a field oxide film 19. Drain region 11 is also formed in a region surrounded by word line 13 and field oxide film 19.
The operation of the NOR type flash memory having the above described structure will be described with reference to FIG. 150.
In writing operation, a voltage of 5V is applied to drain region 11 and a voltage of about 10V is applied to control gate 13. Source region 12 and p type impurity region 10 are kept at the ground potential (0V). At this time, a current of several 100 .mu.A flows through the channel of the memory transistor. Among the electrons flowing from the source through the drain, electrons accelerated near the drain turn to be electrons having high energy in the vicinity, that is, so called channel hot electrons. These electrons are introduced to floating gate 14 as denoted by the arrow 1 because of the electric field generated by the voltage applied to control gate 13. In this manner, electrons are stored in floating gate 14 and the threshold voltage Vth of memory transistor attains, for example, 8V. This state is called the written state, that is, "0".
In the erasing operation, a voltage of about 5V is applied to source region 12, a voltage of about -10V is applied to control gate 13 and p type impurity region 10 is held at the ground potential. Drain region 11 is released. Because of the electric field caused by the voltage applied to source region 12, electrons in floating gate 14 pass through thin gate oxide film 15 by tunnelling phenomenon, as shown by the arrow 2. As electrons in the floating gate 14 are drawn out in this manner, the threshold voltage Vth of the memory transistor attains, for example, to 2V. This state is referred to as erased state "1". Since the source of each memory transistor is connected as shown in FIG. 149, all memories can be erased at one time by this erasing operation.
In reading operation, a voltage of about 5V is applied to control gate 13 and a voltage of about 1V is applied to drain region 11. Source region 12 and p type impurity region 10 are kept at the ground potential. At this time, determination of "1" or "0" is carried out dependent on whether a current flows through the channel region of the memory transistor.
More specifically, in the written state, there is no channel formed as Vth is 8V, and therefore current does not flow. In the erased state, a channel is formed and current flows, as Vth is 2V. In the NOR type device, electrons are introduced to the floating gate 14 utilizing channel hot electrons so as to realize the written state "0". Since introduction of electrons using channel hot electrons is not very efficient, power consumption of the NOR type device is large.
Referring to FIG. 152, when memory transistor 22a is selected and writing is to be done in this transistor, for example, a voltage of about 5V is applied to drain region 11, and a voltage of about 10V is applied to control gate 13 as described above, and writing is done in the floating gate 14 of the memory transistor 22a.
When memory transistor 22b is selected for writing, similar voltages are applied to drain region 11 and control gate 13 of memory transistor 22b. Since memory transistors 22a and 22b share the drain region 11, there is a possibility that electrons which have been introduced to floating gate 14 of memory transistor 22a are drawn out to drain region 11 by tunneling phenomenon, because of the voltage applied to drain region 11 at the time of writing to memory transistor 22b. This phenomenon is called drain disturb phenomenon. Since electrons are drawn out from the floating gate of the memory transistor to which electrons are introduced because of the drain disturb phenomenon, the memory transistor which must have been the written state turns to be to the erased state, which causes erroneous operation of the flash memory.
A NAND type device has been proposed to solve the problems in the NOR type. The NAND type flash memory is disclosed, for example, in Nikei Electronics 1992. 2. 17 (No. 547), pp. 180 to 181. FIG. 153 is an equivalent circuit diagram of a portion of the NAND type flash memory. Select gate transistors 39a, 39b and 39c have one impurity region connected to the bit line and the other impurity region connected to memory transistors 38a, 38b and 38c, respectively.
By select gate transistors 39a, 8 memory transistors 38a arranged in the lengthwise direction are selected; by select gate transistors 39b, 8 memory transistors 38b arranged in the lengthwise direction are selected; and by select gate transistors 39c, 8 memory transistors 38c arranged in the lengthwise direction are selected. These memory transistors 38a, 38b and 38c are grounded through select gate transistors 23a, 23b and 23c, respectively.
FIG. 154 is a cross section of a part of the memory cell matrix of the NAND type flash memory. At a P type impurity region 30 formed in the silicon substrate 26, impurity regions 27 are formed spaced apart from each other. Between the impurity regions 27, a memory transistor 38a having a floating gate 29 and a control gate 28 is formed.
FIG. 155 is a cross section of memory transistors 38a. At a p type impurity region 30 formed in silicon substrate, impurity regions 27 are formed spaced apart from each other. At the p type impurity region 30 between the impurity region 27, a gate oxide film 35, a floating gate 29, an interlayer insulating film 36 and a control gate 28 are stacked. Control gate 28 and floating gate 29 are covered by an oxide film 37.
The operation of the NAND type flash memory will be described with reference to FIGS. 153 to 155. First, writing operation will be described. When writing is to be done in the memory transistor 38a having the word line W.sub.8, for example, selecting gate S.sub.2 of select gate transistor, bit line B1, source line and p type impurity regions 30 are kept at the ground potential, a voltage of about 10V is applied to S.sub.1, B2 and B3, a voltage of about 20V is applied to word line W.sub.8, and other word lines W.sub.1 to W.sub.7 are kept at the ground potential. Consequently, as shown by 1 in FIG. 155, in the memory transistor 38a having the word line W.sub.8 (control gate 28), electrons in the channel region are introduced to floating gate 29 by channel FN. This corresponds to the written state "0", and V.sub.th at this time is 3V.
The erasing operation will be described. For erasure, a voltage of 20V is applied to the bit line S.sub.1, S.sub.2 and p type impurity region 30, and word lines W.sub.1 to W.sub.8 are kept at the ground potential. At this time, electrons are drawn out from the floating gate 29 of memory transistor 38a which is at the written state "0" to the channel region by channel FN, and it is set to the erased state "1". V.sub.th at the erased state "1" comes to be -2V.
The reading operation will be described. When reading of memory transistor 38a having the word lines W.sub.8 is to be carried out, a voltage of about 1V is applied to bit line B1, and the source line and the substrate are kept at the ground potential. Word line W.sub.8 is kept at the ground potential and a voltage of about 5V is applied to word lines W.sub.1 to W.sub.7. A prescribed voltage is applied to selecting gates S.sub.1 and S.sub.2 to turn ON the select gate transistor.
Since word line W.sub.8 is kept at the ground potential (0V), when the memory transistor 38a having the word line W.sub.8 is at the erased state "1", memory transistor 38a is turned ON, while if it is at the written state "0", memory transistor 38a is turned OFF. Memory transistors 38a having word lines W.sub.1 to W.sub.7 are turned ON regardless of the written state "0" or erased state "1", as a voltage of 5V has been applied to word lines W.sub.1 to W.sub.7.
Therefore, referring to FIG. 154, when the memory transistor 38a having the word line W.sub.8 is at the erased state "1", the current flows through a channel formed by respective word lines W.sub.1 to W.sub.8, through the bit line to the sense amplifier. When memory transistor 38a having word line W.sub.8 is at the written state "0", since there is no channel form by word line W.sub.8, current does not flow to the sense amplifier. Therefore, when sense amplifier senses a current, it is determined to be the erased state "1", while if the current is not sensed, it is determined to be the written state "0".
When electrons are introduced to the floating gate utilizing channel FN, efficiency is higher as compared with the case when electrons are introduced by using channel hot electrons. Therefore, compared with the NOR type device, power consumption in the NAND type device can be reduced.
Further, since a high voltage is not applied to the drain region of the memory transistor as channel FN is used in writing in the NAND type device, the drain disturb phenomenon can be prevented.
However, in the NAND type device, since reading is carried out by a current flowing through 8 memory transistors arranged in series, the time necessary for reading operation is long.
In addition, since a relatively high voltage of 20V is used in writing and erasing, higher degree of integration is difficult.